Presented by Prateek Mishra

November 19, 2008

H. Chang and S. Sapatnekar "Full-Chip Analysis of Leakage Power under Process Variations, including Spatial Correlations," DAC '05

Presented by Niket Agarwal

November 12, 2008

S. Sankar, S. Gurumurthi, and M. Stan "Intra-Disk Parallelism: An Idea Whose Time Has Come," ISCA '08

Presented by Carole-Jean Wu

October 15, 2008

E. Ipek et al. "Self-Optimizing Memory Controllers: A Reinforcement Learning Approach," ISCA '08

Presented by Jakub Szefer

October 1, 2008

G.E. Suh et al. "Design and Implementation of AEGIS: Single-Chip Secure Processor Using Physical Random Functions," ISCA '05

Presented by Carven Chan

April 2, 2008

Asanović, Krste, "Transactors for parallel hardware and software co-design," High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International , vol., no., pp.140-142, 7-9 Nov. 2007

Hoe, J.C.; Arvind, "Operation-centric hardware description and synthesis," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.23, no.9, pp. 1277-1288, Sept. 2004

Presented by Abhishek Bhattacharjee

March 12, 2008

A. Bhattacharjee, M. Martonosi, "," submitted to ISLPED ‘08

Presented by Yu-Yuan Chen

Febuary 20, 2008

W. Shi, H. S. Lee, L. `Falk and M. Ghosh, "An integrated framework for dependable and revivable architectures using multicore processors," in ISCA '06: Proceedings of the 33rd Annual International Symposium on Computer Architecture, 2006, pp. 102-113.

Presented by Daniel Schwartz-Narbonne

Febuary 13, 2008

T. M. Austin and T. M. Austin, "DIVA: A reliable substrate for deep submicron microarchitecture design," in Microarchitecture, 1999. MICRO-32. Proceedings. 32nd Annual International Symposium on, 1999, pp. 196-207.

Presented by Bin Li

Febuary 6, 2008

L. Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian and J. B. Carter, "Interconnect-Aware Coherence Protocols for Chip Multiprocessors," SIGARCH Comput. Archit. News, vol. 34, pp. 339-351, 2006.

Presented by Carole-Jean Wu

Janurary 31, 2008

K. J. Nesbit, J. Laudon and J. E. Smith, "Virtual private caches,Presented at ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture.

Presented by Abhishek Bhattacharjee

Janurary 24, 2008

C. Isci and M. Martonosi, "Runtime power monitoring in high-end processors: Methodology and empirical data," in Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on, 2003, pp. 93-104.

Presented by Niket Agarwal

Janurary 15, 2008

M. M. K. Martin, M. M. K. Martin, M. D. Hill and D. A. Wood, "Token coherence: a new framework for shared-memory multiprocessors," IEEE Micro, vol. 23, pp. 108-116, 2003.

M. M. K. Martin, M. M. K. Martin, M. D. Hill and D. A. Wood, "Token coherence: Decoupling performance and correctness," in Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on, 2003, pp. 182-193.

ISCA presentation

Presented by Konstantinos Aisopos

Janurary 8, 2008

Alameldeen,A.R.; Wood,D.A. “Adaptive cache compression for high-performance processors.

Alameldeen,A.R.; Wood,D.A. “Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches.