Dr. Joel S. Emer

Joel S. Emer is an Intel Fellow, Digital Enterprise Group, and Director of Microarchitecture Research.

Emer joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel. Prior to joining Intel, Emer was a Compaq Fellow and Director of Alpha Architecture Research, where he led research efforts for future processors for Compaq's 64-bit family of servers.

With over 25 years of combined service to Compaq and Digital Equipment Corporation, Emer has held various research and advanced development positions investigating processor microarchitecture designs and developing performance modeling and evaluation techniques. Emer is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of simultaneous multithreading technology. He holds 15 patents and has published more than 30 papers.

Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. Emer earned a doctorate in electrical engineering from the University of Illinois in 1979.

Dr. Pradip Bose

Pradip Bose received his B. Tech. degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India in 1977 and the M.S. and Ph.D degrees in Electrical and Computer Engineering from the University of Illinois, Urbana-Champaign, in 1981 and 1983 respectively. Since May 1983, Dr. Bose has been a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. During 1992-94, Dr. Bose was on assignment at IBM Austin, where he served as the lead performance engineer during the definition and evaluation of a processor, which eventually evolved into IBM's POWER3 microprocessor. During the 1989-90 academic year, Dr. Bose was a Visiting Associate Professor at Indian Statistical Institute, Calcutta, India as part of a sabbatical leave assignment from IBM. During that year, he worked on the application of artificial intelligence techniques to problems in VLSI CAD. His current research interests include: high performance computer architectures and their performance evaluation, verification and testing.

Dr. Rajiv Joshi

Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech degree from Indian Institute of Technology (Bombay, India), M.S degree from Massachusettes Institute of Technology and Doctorate in Eng. Science from Columbia University, USA. From 1981 to 1983, he with GTE research lab in Waltham, Massachusettes. He joined IBM in Nov. 1983, and since then is working in VLSI design systems, science and technology. He worked on 1.25mm NMOS, and CMOS, sub-0.5mm CMOS logic, DRAM and SRAM technologies. He developed novel interconnect processes and structures for Aluminum, tungsten and Copper technologies which are widely used in IBM for various sub-0.5mm memory and logic technologies as well as across the globe. His circuit related work includes design of register files, registers, latches, L1 caches-directory, TLB, IO circuits development of physical design tools, and CAD based library generation and circuit designs in SOI technology. He contributed to S/390 Alliance processor design, working in both circuit design and CAD tools. The Alliance G5 chip was a very successful IBM product and Joshi received IBM Research Division Awards for his contributions to it and each of the follow-on processor designs. He jointly published paper with IBM Poughkeepsie team on 2 GHz SRAM in G6 processor, which received worldwide attention. He received an Outstanding technical achievement award for his contributions to G6. He contributed through IP and designs to IBM PowerPC program taking leadership role in SRAM technology, cell analysis/modeling and stability enhancement. He led successfully the Technology driven SRAM at IBM Server Group. He has won 46 invention plateau achievement awards from IBM and won two divisional patent portfolio awards for cross-licensing and utilization of his patents in the IBM products. He has received 5 Research Division Awards, and several top 10% patent awards (for licensing activities). He received three Corporate Patent Portfolio awards from IBM for licensing contributions (June 6, 2002 and May 26, 2004, May 15 2007). He is a master inventor & key technical leader at IBM research division. He has authored and co-authored over 128 research papers and presented several invited and keynote talks. He holds 128 U.S. patents in addition to several pending patents. He received the Lewis Winner Award in 1992 for an outstanding paper he coauthored at the International Solid State Circuit Conference. He was instrumental in starting interconnect workshop in early 1980s. He chaired advanced interconnect conferences sponsored by MRS and served as an editor of the proceedings. He is elected as an IEEE fellow for 2002 for contributions to chip metallurgy materials and processes, and high performance processor and circuit design. He is a recipient of “Distinguished Alumnus Award” in the year 2008 from IIT, Bombay. He is actively involved in IEEE ISLPED (Int. Symposium Low Power Electronic Design) IEEE VLSI design, IEEE Int. SOI conf (2000-2003), ISQED Program committees.

Partha Kundu

Partha Kundu is a senior staff research Scientist within Intel's Microprocessor Technology Labs (MTL) in Santa Clara, California. He was an architect of the Intel® Itanium® architecture and a Principal Architect on a DEC/Alpha microprocessor. His research interests include on-chip networks, memory system design, transactional memory, and performance simulation. He holds an M.S. degree from the State University of New York, Stony Brook.

Prof. Todd Austin

Todd Austin is an Associate Professor of Electrical Engineering and Computer Science at the University of Michigan in Ann Arbor. His research interests include computer architecture, reliable system design, hardware and software verification, and performance analysis tools and techniques. Prior to joining academia, Todd was a Senior Computer Architect in Intel's Microcomputer Research Labs, a product-oriented research laboratory in Hillsboro, Oregon. Todd is the first to take credit (but the last to accept blame) for creating the SimpleScalar Tool Set, a popular collection of computer architecture performance analysis tools. In addition to his work in academia, Todd is co-founder of SimpleScalar LLC and InTempo Design LLC. In 2002, Todd was a Sloan Research Fellow, and in 2007 he received the ACM Maurice Wilkes Award for "for innovative contributions in Computer Architecture including the SimpleScalar Toolkit and the DIVA and Razor architectures." Todd received his Ph.D. in Computer Science from the University of Wisconsin in 1996.

Dr. David Safford

David Safford is a researcher at IBM's T.J. Watson Research Center in Hawthorne, New York. He published his first ethical hack in 1981, and led IBM's ethical hacking team through 2005. His current research is in Linux adoption of trusted computing, and in CPU architectures for secure computing. Prior to IBM, he was Director of Supercomputing for Texas A&M University, was a nuclear submarine Diving Officer and weapon system test pilot in the US Navy. He is also one of the authors of A Practical Guide to Trusted Computing.

Prof. Scott Mahlke

Scott Mahlke is an Associate Professor in the Electrical Engineering and Computer Science Department at the University of Michigan. He is affiliated with the Advanced Computer Architecture Laboratory and the Software Systems Laboratory. He works in the areas of Compilers and Computer Architecture. He joined Michigan in 2001 after receiving his Ph.D. from the University of Illinois and working at HP Laboratories.