Detailed Group Results

GROUP 1

# include (std. - Disclaimer)

Q1: Main Theoretical Contributions:

1. Quine - McClusky Method
2. Shannon/Boole Decomposition
3. Exact Timing Analysis
4. State Minimization of Incompletely specified state machines
5. Don't Cares

Q2: Main Practical Contribution:

1. Decision Diagram Data structure
2. Retiming
3. Heuristic Multi-level Minimization
4. Tree Mapping
5. RTL --> Logic

Q3: Controversial Issues

1. [A-Z]*[d-W]*[.3-T-2T]*DDs
2. Spectral Transformation/RM xformation
3. Overselling of Power
4. Overselling of Synth. of Asynchronous
5. Use of PROLOG for Logic Synthesis/Verification

Q4: Contributions From This Workshop.

1. Advances in solution for SAT/covering problems
2. DSM/Combinational/Sequential/Logic/Physical Synthesis

1. VUDSM
2. Layout Driven Synthesis
3. Chipp Level Verification
4. New Circuit Families
5. Noise Issues
6. Synthesis for Manufacturability, Reliability
7. Hardware Reuse
8. Java (TM) based distributed design flow.
9. Quantum Computing
10. DNA computing (look at us)

GROUP 2

Q1: Five Most Important Theoretical Contributions

1. Theory of Algebraic Optimization
2. Implicit Set Manipulation
3. Theory of Flexibility in Logic Optimization
4. Multifault Testability
5. False Path Analysis

Q2: Five Most Important Practical Contributions

1. Major Milestones in Logic Synthesis Tools: - LSS => MIS/SIS => Synopsys Design Compiler
2. BDD Methods
3. Practical Research Environment: - Availability of University S/W / Standard Languages/Benchmarks/IWLS
4. Espresso and Heuristic Minimization
5. SAT Solvers

Q3: Three Most Useless Subjects

1. Reargued, Unscalable Research Directed Specifically at Bogus Benchmarks - Optimization of 10 State FSMs - (Bad) Research in Low Power at the Gate Level
2. VERILOG/UHDL Split

Q4: Three Most Important subjects at IWLS 97

1. DSM
2. Timing Analysis
3. Satisfiabiity and Covering

Q5: Three Most Important Subjects at IWLS 02

1. IP/System on a Chip
2. VDSM
3. Synthesis Methodology for Verifiability

GROUP 3

Group 4

Q1: 5 Most Important Theoretic Contributions

1. Expresso/Quine - McCluskey
2. BDDs (Bryant)
3. Application of Computation Complexity
4. See contribution #5.
5. See contribution #6.

Q2: 5 Most Important Practical Contributions

1. BDD Algorithms
2. Implication Methods and Other ATPG Algorithms (Recursive Learning, Redundancy Addition/Removal)
3. 2-Level Optimization (Expresso)
4. Public Domain Software (*IS, BDD Packages)
5. Technology Mapping and Post-Mapping Optimization (Socrates, LUT-Based Packages)

Q3: 3 Most Useless Issues in the Last 10 Years

1. Experimental Noise Dominating the Accuracy of the Mode (Delay Models, Power Analysis, Retiming)
2. Misleading and Misinterpreted Experimental Results => Need for CAD Community to be More Accepting of Negative Results (Within Reason)
3. Overuse and Overgeneralization of BDDs (E.g., Canoncity of BDDs Not Required for the Problem, "Alphabet Soup of BDDs" - Randal Bryant)

Q4: 3 Most Important Issues at IWLS/97

1. BDDs and Applications
2. Pass Transistors
3. Functional Verification

Q5: 3 Most Important Subjects at IWLS - 2002

1. Design Convergence (Physical Design and Logic Synthesis)
2. Interface Analysis and Modeling for IP Design
3. Managing/Abstracting Large Designs
4. Web-Based Design
5. Focus Group Speaker Designation Avoidance

Group 5

Q1: Theoretical Contributions

Given Seminal Work on Models

1. Quine - McCluskey
2. Algebraic Decomposition - (Exponential Reductions)
3. Transduction Method - (Link Structure and Function)
4. Symbolic Minim and Constrained Enc. - (Need FSMs)
5. BDDs - (Efficient Canonical Pepr.)

Practical Contributions Given

1. Lots of Useful/less Theory
2. Express
3. Tree-Based Techmap
4. MIS IN Pubic Domain - (Otherwise No synopsys)
5. Efficient Impl. of BDDs/Sifting - (Otherwise Can't Beat Synopsys)
6. Retiming - Neat, Polynominal...)

Q2: Useless Subjects

1. Asynchronous Circuits Would Win Now But Nobody Ready To Bet On It
2. Lower Power Logic Synthesis - (Minimal Improvement, Questionable Model/Cost Function)
3. False Paths - (Nobody uses It, Although It's Neat...)
4. Genetic Algorithms - (Orgies and Immoral...)

1. Interaction B/W Synthesis ad Physical Design - (Can't Decouple)
2. System-Level Interface Design - (Should Decouple...)
3. Feedback From Designers - (Did You See Any?)

Q3: 5 Years From Now

1. Interaction B/W Synthesis & Physical Design - (Controversial...)
2. Communication Synthesis - (IP Integration - What A Lovely Keyword)
3. Reconfigurable Logic - (Need Something Well...) Loo, Ma... No BDDs!

Group 6

Q1: Most Important Theoretic Contributions

1. Two-level Logic Minimization
2. Multi-level Logic Optimization, Algebraic Transform
3. BDD's, Representations of Logic functions
4. Timing Analysis, False Paths
5. Don't Cares, Boolean Optimization Techniques

Q2: Most Important Practical Contributions

1. FPGA's, Concept, Tools
2. Tools for 2-level Minimization (express)
3. Tools for Multi-level synthesis (MIS, SIS)
4. Delay Models, Performance Optimization Techniques
5. BDD Packages

Q3: Most Useless Subjects

1. Theory for Power Estimation/Reduction in Logic Synthesis
2. Exotic BDD's (Too Many!)
3. ISCAS Benchmarks (*)

Q4: Most Important Issues Presented at IWLS '97

1. Efficient Solutions to Basic Problems - (SAT, Covering, Coloring, ILP)
2. Layout-oriented Synthesis, Integration
3. Alternative Design Styles - PTL, Domino

Q5: Topics for IWLS' 2002

1. Drastically New Design Methodology
2. Linking Logic with layout, Integration
3. Moving Toward Full Custom, Transition Level Design Styles

Group 7

Q1: Theoretical Contributions

1. Sequential Optimization (State Assignment, DeMicheli, Retiming, Leiserson/Taxe)
2. Two-level and Multi-level Logic Minimization - Quine-McClusky, ODC-based node simplification, ATPG-based Techniques)
3. Kernel Extraction - (Brayton and McMullen)
4. Verification - (Combinational, Automated-based)
5. Binary Decision Diagrams and Some of Its Variants - (Acker, Bryant, etc.)

Q2: Practical Contributions

1. Technology Mapping
2. Espresso/MIS
3. BDD-based Algor
4. Redundancy Removal Techniques
5. Retiming

Q3: Overvalued Concepts/Algorithms

1. Too Many Variants on BDD's
2. Parallel Cad Algorithms
3. Expert Systems for CAD

Q4: Best IWLS Papers

1. Paper 3 in Session 3 (DDs and PTL)
2. ?

Q5: Future Areas of Interest

1. Links Between Physical Design and Logic Synothesis
2. Hierarchical/Incremental Synthesis
3. Mixed-domain Systems (Analog, Digital, Mechanical, etc.)

Group 8

Q1: Five Most Important Theoretical Contributions

1. Boolean Algebra
2. Two-level Logic Optimization
3. Algebraic Methods of Multi-level - Logic Synthesis
4. Complexity Theory
5. BDD - Automata Theory

Q1: Five Most Important Practical Contributions

1. Interactive Synthesis Tool
2. BD Package
3. Technology Mapping
4. ATPG
5. "Library-based" Design - ASICs, Programmable Devices

Q2: Three Most Useless Subjects

1. UDL/1
2. Hardware Accelerator
3. Parallel Algorithms

Q3: Three Most Important Issues at IWLS '97

1. The "Interaction" between Logic Synthesis and Physical Design
2. Verification
3. Functional Decomposition

Q4: Three Most Important Subjects in 2002

1. Intellectual Property
2. Application of Logic Synthesis to Other Areas and New Devices
3. New Application of Data Structure

Group 9

Q1: Theoretical Contributions

1. Boolean Calculus
2. Switching Theory (Shannon)
3. Quine-McClusky EII Minimization
4. Automata Theory
5. Implicit Techniques in Set/Relation Manipulations

Q2: Practical Contributions

1. Algebraic Decomposition Applied to Technology Independent Multi-level Logic Synthesis
2. Technology Mapping
3. BDDs (ROBDDs)
4. Hardware Description Languages
5. 2-Level Logic Minimization

Q3: Useless Stuff - Not So Useful Disclaimer: Views expressed in this slide are not my own. Please sue my team members for and grief caused.

1. Logic Synthesis for Low Power - 5% Power Deduction in 10% Power Component - XW -> 0.995 XW
2. State Encoding/Minimization - Who Uses It?
3. Alphabet Soup of BDDs - ???? BDD (26x26x26x26 > 100,000)

Q4: Important Issues At This Symposium

1. Logic Synthesis for High Performance
2. Link Between Logic Synthesis and Physical Design
3. Search Techniques

Q5: Issues for IWLS 2005

1. Modeling Physical Effects at the Logic Level - (Wiring Cost, Noise, Wiring Delay)
2. Support for Design Reuse/Design Change
3. Support for Efficient Design Validation at Higher Levels of Abstraction

Group 10

Q1: Looking Back

Theory

1. Karnaugh Maps. Q-M
2. Unate Recursive Paradigm
3. Dynamic Prog. Tree Cover
4. Data Structures for Boolean Functions
5. FSM and Language Based Design

1. Espresso
2. Dagon/MIS
3. *BDD packages
4. RTL Synthesis

Q2: Now

Important

1. FPGA Based SAT
2. Change Tools
3. Synthesis and Physical Design Papers?
4. Synthesis of Non-Static CMDS

Useless

1. Graphical FSM Design - Not Useful Enough to
2. Synthesis for Low Power Not the Way to Get Real Savings
3. Design for Test/Synthesis for Test, Is This the Right Problem Tomorrow? Today?

Q3: Looking Forward - 2002

Hierarchy

Design

1. Blocks
2. Functions
3. Subroutines

1. Re-encode signal/bus - Physical Issues - H/S Co-Synthesis
2. Timing disciplines ( Sync + Async + ...)
3. Verification Functional and Timing