EE 470: Spring '00

Configurable Computing: An Overview

Lecture notes #1

Course Structure and Administrivia

The course meets twice a week. Some lectures will be given by me, and others will be given by students in the class. Discussion questions and reading assignments will be placed on the web before the lecture they pertain to. Please read the assigned papers and be ready to discuss the issues raised in the discussion questions. Since the physical act of writing down your own notes is an important part of learning, I won't be distributing lecture notes beforehand. Rather, I'll put my own sketches of notes out on the web after lecture. No promises of completeness--you should take your own notes in order to be sure you're getting everything.

Lecture Notes

What is Configurable computing?

Customizing computation to a particular application by changing hardware functionality on the fly.
Increasing in popularity due to improvements in the size and speed of programmable hardware devices.

Why Configurable Computing?

To improve performance over a software implementation

e.g. signal processing apps in configurable hardware

To improve product flexibility compared to hardware

e.g. encryption or network protocols in configurable hardware

To use the same hardware for different purposes at different points in the computation!

Promising Configurable Computing Application Areas:

Signal processing
Encryption
Low-power (through hardware "sharing")
Variable precision arithmetic
Logic-intensive applications
In-the-field hardware enhancements
Adaptive (learning) hardware elements

Overall approach:

Select portions of an application where hardware customizations will offer an advantage
Map those application phases to FPGA hardware

hand-design
VHDL => synthesis

If it doesn't fit in FPGA, re-select application phase (smaller) and try again.
Perform timing analysis to determine rate at which configurable design can be clocked.
Write interface software for communication between main processor and configurable hardware

Determine where input / output data communicated between software and configurable hardware will be stored
Write code to manage its transfer (like a procedure call interface in standard software)
Write code to invoke configurable hardware (e.g. memory-mapped I/O)

Compile software (including interface code)
Send configuration bits to the configurable hardware
Run program.

Application Challenges:

This process turns applications programmers into part-time hardware designers!
Automate!

Performance analysis problems => what should we put in hardware?
Hardware-Software Co-design problem
Synthesis problems
Testing/reliability problems

We'll look at much of this during this class.

Common Configurable Architecture Today:

FPGA array on board connected to I/O bus Common Configurable Architecture Tomorrow:

Currently FPGAs and configurable computing go hand-in-hand, but that needn't be the case.

Other possibilities:

Integrate configurable hardware onto DRAM chip=> Flexible computing without memory bottleneck Technology Trends Driving Configurable Computing:

Increasing gap between "peak" performance of general-purpose processors and "average actually achieved" performance.

Most programmers don't write code that gets anywhere near the peak performance of Alpha 21164 or Pentium Pro

Improvements in FPGA hardware: capacity AND speed

FPGAs use standard SRAM processes and "ride the commodity technology" curve
volume pricing even though customized solution

Improvements in synthesis and FPGA mapping/routing software
Increasing number of transistors on a (processor) chip: How to use them all?

bigger caches
multiple processors
FPGA!

Hardware Software Spectrum

Custom hardware => Gate Arrays => FPGAs => General-purpose microprocessors running statically compiled code => General-purpose microprocessors running dynamically compiled code What makes an application well-suited for a configurable implementation?

Contrast Dynamic (or data-specific) Compilation (a la Java) with Configurable Computing

FPGAs

Field programmable gate arrays
Chip contains many small building blocks that can be configured to implement different functions
These building blocks are known as CLBs (Configurable Logic Blocks)
FPGAs typically "programmed" by having them read in a stream of configuration information from off-chip

That is, they are typically in-circuit programmable
(As opposed to EPLDs which are typically programmed by removing them from the circuit and using a PROM programmer)

25% of an FPGA's gates are application-usable

The rest control the configurability, etc.

as much as 10X clock rate degradation compared to custom hardware implementation
Typically built using SRAM fabrication technology

FPGA Capacities and Speeds

How do FPGAs work?

Programming/Configuring FPGAs

Software (e.g. XACT or other tools) converts a design to netlist format.
XACT:

partitions the design into logic blocks
then finds a good placement for each block and routing between them (PPR)

then a serial bitstream is generated and fed down to the FPGAs themselves
The configuration bits are loaded into a "long shift register" on the FPGA.
The output lines from this shift register are control wires that control the behavior of all the CLBs on the chip.

Some more points on programming/configuring:

Since FPGAs "act" like SRAM or logic, they lose their program when they lose power.
Configuration bits need to be reloaded on power-up.
Usually reloaded from a PROM, or downloaded from memory via an I/O bus.

What does a CLB look like?

Xilinx...
Others...
Example of implementing a particular function in a CLB

Hardware Challenges in using FPGAs for Configurable Computing

Configuration overhead
I/O bandwidth
speed, power, cost, density

Other Challenges

High-level language support
Performance, Space estimators
Design verification
Partitioning and mapping across several FPGAs