Subject: Intel Architecture 64-bits Software Technologies Published: November 22, 1999 Compilers An Overview of the Intel IA-64 Compiler Tools SoftSDV: A Pre-silicon Software Development Environment for the IA-64 Architecture Assembly Language Programming Tools for the IA-64 Architecture Operating System Ports Porting Operating System Kernels to the IA-64 Architecture for Pre-silicon Validation Purposes Floating Point The Computation of Transcendental Functions on the IA-64 Architecture IA-64 Floating-Point Operations and the IEEE Standard for Binary Floating-Point Arithmetic	The Challenges of New Software for a New Architecture — Richard Wirt, Intel Fellow and Director of the MicroComputer Software Labs			Lin Chao Editor Intel Technology Journal With the close of the year 1999, it is appropriate that we look forward to Intel's next generation architecture--the Intel Architecture (IA)-64. The IA-64 represents a significant shift for Intel architecture: it moves from 32-bits to 64-bits. Targeted for production in mid-2000, the Itanium™ processor will be the first IA-64 processor. One of Intel's key aims is to facilitate a transition of this magnitude. To this end, Intel and key industry suppliers are working to ensure that a complete set of "ingredients" is available for the IA-64 architecture. This includes operating systems, compilers, and application development tools that are "64-bit capable." In this issue of the Intel Technology Journal, you will learn about Intel's efforts in IA-64 software technology. In the first papers, Intel's own IA-64 compiler efforts are discussed. The first paper gives an overview of Intel's production compiler, code named "Electron." We then move to the second and third papers where software development tools for the IA-64 architecture are discussed. As is often the case with a brand new architecture, software companies start developing software in advance of actual hardware. SoftSDV (a software-based system development vehicle) is a tool that simulates IA-64 hardware platforms in lieu of actually having the hardware. This tool assists engineers in porting commercial operating systems and applications to the IA-64. Intel's IA-64 Assembler is described in the fourth paper. The Assembler can simplify IA-64 assembly language programming. Validation is a critical function in the testing of new circuits such as those on IA-64 silicon. The fourth paper describes the porting of the Linux* and Mach* operating systems and how they run on software simulators to exercise operating system related functionality in the IA-64 architecture. The final two papers discuss the floating-point functions on the IA-64 architecture. Fast and accurate computation of transcendental functions (e.g. sin, cos, and exp) and the implementation of floating-point operations are also discussed. We welcome your comments about the Journal and its papers.
	Compilers An Overview of the Intel IA-64 Compiler By Carole Dulong, Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel Lavery ,Wei Li , John Ng, and David Sehr The IA-64 architecture features expose new opportunities for the compilers to optimize applications. Intel's IA-64 compiler incorporates many key optimization techniques to boost the performance of applications on the IA-64 hardware. In this paper, we provide an overview of the Intel IA-64 compiler, discuss and illustrate several optimization techniques, and we explain how these optimizations help harness the power of IA-64 for higher application performance. Tools SoftSDV: A Pre-silicon Software Development Environment for the IA-64 Architecture By Richard Uhlig, Roman Fishtein, Oren Gershon, Israel Hirsh, and Hong Wang The traditional approach to fostering software development for a new instruction set is to supply programmers with a hardware platform using the new instruction set. Such a platform is commonly known as a software-development vehicle (SDV). This paper describes how Intel eliminated this dependency for IA-64 hardware by building an SDV entirely in software through the simulation of all processor and IO-device resources present in an actual hardware IA-64 SDV. This simulation environment, called SoftSDV, has enabled substantial development of IA-64 software, well in advance of Itanium processor's first silicon. Assembly Language Programming Tools for the IA-64 Architecture By Ady Tal, Vadim Bassin, Shay Gal-On, and Elena Demikhovsky The IA-64 architecture incorporates many features that enable assembly programmers to optimize their code for efficient, high-sustained performance. This paper describes Intel's IA-64 Assembler and IA-64 assembly assistant tools, which can simplify IA-64 assembly language programming. The descriptions of the tools are accompanied by examples that use advanced IA-64 features. Operating System Ports Porting Operating System Kernels to the IA-64 Architecture for Pre-silicon Validation Purposes By Kathy Carver, Chuck Fleckenstein, Joshua LeVasseur, and Stephan Zeisset One of the major goals for early hardware of a new architecture is to boot a commercial operating system shortly after the arrival of first hardware systems. Intel's IA-64 team decided to use an operating system kernel for pre-silicon validation of the new IA-64 Itanium (tm) processor in addition to using conventional pre-silicon testing methods. Therefore two operating system kernels were ported to provide additional vehicles for pre-silicon validation and post-silicon debug. The Mach*3 microkernel was ported first, followed by the Linux* 2.2.0 kernel. These operating system kernels also helped pre-silicon performance analysis and compiler-generated code analysis. Floating Point The Computation of Transcendental Functions on the IA-64 Architecture By John Harrison, Ted Kubaska, Shane Story, and Ping Tak Peter Tang The fast and accurate evaluation of transcendental functions (exp, log, sin, and atan) is vitally important in many fields of scientific computing. Transcendental functions can be computed in software by a variety of algorithms. This paper discusses some of the design principles and implementation details of double-precision transcendental functions that are highly accurate yet can typically be evaluated in between 50 and 70 clock cycles. IA-64 Floating-Point Operations and the IEEE Standard for Binary Floating-Point Arithmetic By Marius Cornea-Hasegan and Bob Norin Compliance with the IEEE Standard for Binary Floating-Point Arithmetic is important for any modern microprocessor. This paper shows how various facets of the IEEE Standard are implemented or reflected in the IA-64 architecture and how the the IA-64 architecture is fully compliant with the IEEE Standard. In addition, this paper shows features of the floating-point architecture that allow for high-accuracy and high-performance computations, while abiding by the IEEE Standard.